1. Field of the Invention
The present invention relates generally to switching voltage regulators and in particular to a control apparatus for accurately controlling switching between a PWM mode and a PFM mode of operation in a multimode buck DC-DC converter.
2. Description of Related Art
Switching voltage regulators are commonly used to provide a regulated voltage source derived from a power source such as a battery. One common type of switching regulator operates as a step down regulator (buck converter) that provides a voltage output which is smaller than the input voltage utilizing pulse width modulation (PWM). FIG. 1 is a simplified diagram of a conventional buck converter, with the control circuitry not being depicted. An inductor L is provided having one terminal connected to the regulated output voltage Vout node. The other terminal of the inductor is connected to the input voltage node Vin by way of a P type transistor switch 22, some times referred to as the high side transistor. The same inductor terminal is connected to ground by way of an N type transistor switch 24, sometimes referred to as the low side transistor. Switches 22 and 24 are driven in opposite phases, with there being a small overlapping OFF period so that Vin in never connected directly to ground through the two switches. The PWM operates at a fixed frequency.
The control circuitry controls the states of P type transistor switch 22 and N type transistors switch 24 to provide a regulated output voltage Vout. The inductor L current is depicted in the timing diagram of FIG. 2. The average inductor current is the same as the load current. As can be seen in the diagram, the load current is such that a DC current flows in inductor L into the load. During an initial switching period T0 to T1, P type transistor 22 is turned ON, while N type transistor 24 is held OFF. During this time period, the voltage across the inductor L is relatively fixed at Vin−Vout. This will cause the inductor current to increase, with the slope of the increasing current equal to (Vin−Vout)/L. This charging current is provided to the filter capacitor C1 and the load represented by RL. Assuming that a voltage-mode architecture is being used, the inductor current will increase until it reaches a peak maximum value IPEAK at time T1.
At this peak current point, a comparator in the control circuitry will trip causing the P type transistor to turn OFF and, after a short overlap period, cause the N type transistor 24 to turn ON. The voltage across the inductor L is now about Vout, with the polarity being such that the inductor L current proceeds to decrease, with capacitor C1 providing the discharge current. The slope of the discharge current from T1 to T2 is −Vout/L. At time T2, the end of one switching cycle, transistor 24 is turned OFF. Given that the load current is assumed to remain relatively constant over a given switching period, the inductor current at the end of a switching cycle T2 is the same as at the beginning of the cycle at T0. This switching is repeated for each successive switching cycle.
The output voltage Vout is regulated by modulating the ON time of transistor 22 (T0 to T2; T2 to T4, etc.) during each fixed duration switching cycle. Thus, if the output voltage Vout should drop due to an increase in load current, the duration of the transistor 22 ON time is increased. Similarly, if Vout should increase due to a drop in load current, the duty cycle of transistor 22 will be reduced.
The average load current is equal to the average inductor L current IAVE. The average inductor current IAVE can be expressed, based upon an inspection of FIG. 2, as follows:IAVE=IDC+(IPEAK−IDC)/2  (1)
When the DC load current IDC approaches zero, equation (1) is reduced to the following:IAVE=IPEAK/2  (2)
Note that N type transistor 24 could be replaced with a simple diode, with the diode becoming forward biased during the discharge of the inductor. However, transistor 24 is implemented using a relatively large device so that the transistor ON resistance is lower than that of a forward biased diode. Thus, under most operating conductions, power consumption is reduced.
Note that if the load current is further reduced from that represented by equation (2), the inductor L will momentarily stop conducting current. In this event, operation switches from what is termed continuous mode operation to discontinuous mode operation. For even lower load currents, it is possible that the inductor current flow will actually reverse direction, with current being pulled from the filter capacitor/load. Since discontinuous mode operation and reverse inductor current can be undesirable in some circumstances, it is possible to avoid this conduction by proper selection of the size of the inductor L and specifying a minimum load current. In order to avoid reverse inductor current flow it is possible to employ a zero inductor current detector which turns transistor 24 OFF just before current in the inductor begins to reverse. The transistor remains OFF during the remainder of the switching cycle at which point transistor 22 is again turned ON.
The above described PWM is relatively efficient, particularly at high and mid-range load current levels. For a typical buck synchronous converter, power loses that can reduce efficiency can be grouped as AC and DC loses, DC loses are determined mainly by the ON resistance of the switching transistor 22 and 24 and by the series resistance of the inductor L. The AC loses, which are proportional to the regulator switching frequency, are primarily due to switching loses and transistor 22 and 24 gate drive loses.
At heavy loads, DC loses predominate so lowering the transistor ON resistances and the inductor resistances are effective in increasing efficiency. However, at light loads, AC loses predominate so that decreasing the switching frequency improves efficiency. As noted above, at low load currents there is a tendency for the inductor current to reverse, which will decrease efficiency so that a zero inductor current detector may be more useful that at high load currents.
It can be seen from the above, that a PWM converter optimized for mid and high load current may not be very efficient at lower load currents. Thus, if a converter is to operate efficiently over a relatively wide range of load currents, including low load currents, some PWM converters utilize multiple operating modes including Pulse Frequency Modulation (PFM). As will be described, PFM is inherently more efficient at low load currents so that efficiency can be increased by switching between PWM and PFM depending upon the load current.
Referring again to the regulator of FIG. 1, PFM is similar to PWM in the sense that transistor 22 can be used to produce a series of inductor current pulses which are applied to the filter capacitor C1 and load Rl. However, the frequency of the pulses in not fixed but rather is varied in order to maintain a regulated output voltage between and upper regulated output voltage level 40A and a lower regulated output voltage 406. The difference between the two regulated voltages depends upon the required accuracy but it is typically less than 1% of Vout. FIGS. 3A/6 and FIG. 4 are timing diagrams that depict operation of what is termed hysteretic PFM. As shown in FIG. 3B, the control circuit (not depicted) operates based upon a maximum peak inductor current level 26 and a minimum (zero) inductor current level 27. The PFM controller initially turns P type transistor 22 ON, with transistor 24 again being held OFF. This causes the inductor current, generally designated by the numeral 27 to increase, starting at zero current with the slope at 27A again being fixed at about (Vout−Vin)/L. At the point the regulated output voltage Vout is located intermediate an upper threshold regulated voltage 40A (FIG. 3A) and a lower threshold regulated voltage 40B, in this case near the lower threshold. This current pulse will cause the output voltage Vout to begin to increase after some delay due to various factors including filter capacitor C1. The magnitude of the voltage increase is related to the load current. This voltage increase is represented by line 30A in FIG. 3A and line 30A in FIG. 4. At this point, the output voltage has not year reached the upper regulated limit 40A.
The inductor current wifi increase over time dt1 to some predetermined upper current limit as indicated by line 26 of FIG. 3B. After the current limit has been reached, transistor 22 is turned OFF followed by transistor 24 turning ON. As indicated by FIG. 3B this will cause the inductor current to drop, with the slope again being about Vout/L. This results in an eventual small drop in the regulated output voltage 31A as shown in FIG. 3A, with the size of the drop being again determined by the size of the load current. A zero inductor current detector will trigger when the inductor current reaches zero indicated by line 28 at the end of the dt2, with this causing transistor 24 to turn OFF followed by transistor 22 turning ON.
The inductor current will then again increase as indicated by 27C of FIG. 3B until the maximum value 26 is reached. In the example of FIG. 3A, this additional current pulse will cause the output voltage to increase to the upper output voltage Vout threshold voltage 40A. In the example of FIG. 4, this additional current pulse is insufficient to increase the output voltage Vout to the upper threshold 40A so that additional current pulses are required which produce additional voltage increases 30C and 30D. At this point, the current pulses supplied by inductor L operate to increase Vout to the upper output voltage Vout threshold. No further current pulses are applied, as indicated by FIG. 3B, since they would cause Vout to go too high. At this point, both drive transistors 22 and 24 are held OFF so that the load current is provided solely by the filter capacitor C1.
The output voltage Vout will begin to drop as capacitor C1 is discharged by the load as indicated by region 42 of the waveform of FIG. 3A. Eventually the output voltage Vout will drop to the lower threshold voltage 40B, at which time additional current pulses are provided as indicated by FIG. 3B thereby causing Vout to increase to the upper threshold voltage 40A. Note that for normal PFM operation at low load currents, inductor current pulses are regularly skipped. A continuous production of inductor current pulses in PFM operation indicates that converter is providing a maximum output current in that mode.
At low load currents, PFM can provide substantially increased efficiency as compared to PWM for the same current output. That is particularly true of the PWM operation has been optimized for efficient mid and high load current operation. By way of example, in the case of PFM operation, no switching losses are present during the dead time 42 previously described. As a further example, because of the zero inductor current detection, transistor 21 can be turned ON with no inductor current present thereby eliminating turn-on losses. Further, the size of the runs ripple current for PWM can vary considerably since it is related to the difference between Vin and Vout, with PFM operation resulting in lower rms inductor currents and thus lower ac inductor losses.
In view of the foregoing, buck converters have been produced having the capability of operating in a PWM mode for mid and high load currents and PFM for low load currents. These converters include provisions for switching between modes based upon the level of the load currents. In some cases the input voltage Vin is further taken in consideration, since PWM efficiency generally decreases as input voltage decreases. Thus, to maximize efficiency, for smaller input voltages it is usually desirable to switch from PWM to PFM at lower load currents. In some applications, the size of the output voltage trout is taken into account with PFM being generally preferred for low output voltage operation.
One prior art approach for switching between PWM and PFM is to monitor the inductor L current flow though P type switching transistor 22, along with monitoring the input voltage Vin magnitude. Since the inductor current provides some indication of the load current, mode switching circuitry operates to switch to PFM operation at low load currents and PWM operation at mid to high load currents. Typically, the maximum operating load current for PFM operation is specified by setting the maximum inductor current Ipeak indicated by line 26 of FIG. 3B. Since the average load current is equal to the average inductor current, the maximum load current for PFM operation is Ipeak/2 assuming that no current pulses are being skipped. If the PFM control circuit causes N number of consecutive current pulses to be produced, where N is typically 32, the converter is considered operating at the specified maximum output current for PFM operation. Thus, the mode control circuitry will cause the converter to switch to PWM. Similarly, when in the mid and high current PWM mode, should the load current drop below a value equal to Ipeak/2, the mode control circuitry will switch to PFM. Thus, increased efficiency is achieved over a wide range of load currents.
It has been found that the above-described approach sometimes results in improper switching between operating modes. By way of example, sometimes the mode control circuitry will detect what is perceived to be low load current conditions and switch from the PWM mode to the PFM mode. While in the PFM mode, this same perceived load current will indicate that the current is sufficiently high to warrant immediately switching back to the PWM. This improper shifting between operating modes under certain operating conditions is obviously undesirable. There is a need for mode control circuitry which is capable of measuring load currents with sufficient accuracy in both the PWM and PFM operation so that this inappropriate shifting between operating modes is either eliminated or substantially reduced. As will become apparent from a reading of the following Detailed Description of the invention together with the drawings, the present invention addresses these and other shortcomings of the prior art.